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Commit 433718e0 authored by Po-Han Chen's avatar Po-Han Chen
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change back to iverilog since the path is fixed

parent a24614e9
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...@@ -89,8 +89,8 @@ def construct(): ...@@ -89,8 +89,8 @@ def construct():
# gate-level simulation use the same VCS node # gate-level simulation use the same VCS node
icarus_sim = Step( this_dir + '/open-icarus-simulation' ) icarus_sim = Step( this_dir + '/open-icarus-simulation' )
rtl_sim = vcs_sim.clone() rtl_sim = icarus_sim.clone()
gl_sim = vcs_sim.clone() gl_sim = icarus_sim.clone()
rtl_sim.set_name( 'rtl-sim' ) rtl_sim.set_name( 'rtl-sim' )
gl_sim.set_name( 'gl-sim' ) gl_sim.set_name( 'gl-sim' )
...@@ -160,7 +160,6 @@ def construct(): ...@@ -160,7 +160,6 @@ def construct():
rtl_sim.extend_inputs(['design.v']) rtl_sim.extend_inputs(['design.v'])
rtl_sim.extend_inputs(['test_vectors.txt']) rtl_sim.extend_inputs(['test_vectors.txt'])
gl_sim.extend_inputs(['design.v'])
gl_sim.extend_inputs(['test_vectors.txt']) gl_sim.extend_inputs(['test_vectors.txt'])
# Connect by name # Connect by name
......
-DUSE_POWER_PINS -DFUNCTIONAL -DUNIT_DELAY=#1 -DSIM -DGL -I /afs/ir/class/ee272/PDKS/sky130A/ /afs/ir/class/ee272/PDKS/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v /afs/ir/class/ee272/PDKS/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v -DUSE_POWER_PINS -DFUNCTIONAL -DUNIT_DELAY=#1 -DSIM -DGL -I /farmshare/classes/ee/272/PDKS.v2021/sky130A /farmshare/classes/ee/272/PDKS.v2021/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v /farmshare/classes/ee/272/PDKS.v2021/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v
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