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Commit 2cefc93e authored by Allen Pan's avatar Allen Pan
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Sram: netgen lvs udpated to use .v netlist as source

parent d6e04a24
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......@@ -41,19 +41,6 @@ saveNetlist -excludeLeafCell \
-phys \
$vars(results_dir)/$vars(design).flatbuslvs.v
saveNetlist -excludeLeafCell \
-flat \
-phys \
-excludeCellInst $lvs_exclude_list \
$vars(results_dir)/$vars(design).nofillerlvs.v
saveNetlist -excludeLeafCell \
-flat \
-flattenBus \
-phys \
-excludeCellInst $lvs_exclude_list \
$vars(results_dir)/$vars(design).nofillerflatbuslvs.v
# Write netlist for Virtuoso simulation
#
......
......@@ -180,8 +180,8 @@ def construct():
pt_power_rtl.extend_inputs(['sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.db'])
pt_power_gl.extend_inputs(['sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.db'])
gdsmerge.extend_inputs(['sky130_sram_1kbyte_1rw1r_32x256_8.gds'])
netgen_lvs_def.extend_inputs(['sky130_sram_1kbyte_1rw1r_32x256_8.sp'])
netgen_lvs_gds.extend_inputs(['sky130_sram_1kbyte_1rw1r_32x256_8.sp'])
# netgen_lvs_def.extend_inputs(['sky130_sram_1kbyte_1rw1r_32x256_8.sp'])
# netgen_lvs_gds.extend_inputs(['sky130_sram_1kbyte_1rw1r_32x256_8.sp'])
calibre_lvs.extend_inputs(['sky130_sram_1kbyte_1rw1r_32x256_8.sp'])
calibre_lvs_nobbox.extend_inputs(['sky130_sram_1kbyte_1rw1r_32x256_8.sp'])
magic_drc.extend_inputs(['sky130_sram_1kbyte_1rw1r_32x256_8.lef'])
......@@ -306,11 +306,11 @@ def construct():
g.connect( dc.o( 'design.sdc' ), pt_timing.i('design.pt.sdc' ) )
# Gate level simulation
g.connect( gl_sim.o( 'run.vcd' ), gen_saif_gl.i( 'run.vcd' ) )
g.connect( signoff.o( 'design.vcs.pg.v' ), gl_sim.i( 'design.vcs.v' ) )
g.connect( pt_timing.o( 'design.sdf' ), gl_sim.i( 'design.sdf' ) )
g.connect( testbench.o( 'testbench.gls.sv' ), gl_sim.i( 'testbench.sv' ) )
g.connect( testbench.o( 'design.args.gls' ), gl_sim.i( 'design.args' ) )
g.connect_by_name( gl_sim, gen_saif_gl ) # run.vcd
# and power signoff
g.connect( signoff.o('design.spef.gz'), pt_power_rtl.i('design.spef.gz' ) )
......
# Set up SRAM instances as black-box cells
model {sky130_sram_1kbyte_1rw1r_32x256_8 inputs/design_extracted.spice} blackbox
model {sky130_sram_1kbyte_1rw1r_32x256_8 design_lvs.spice} blackbox
# model {sky130_sram_1kbyte_1rw1r_32x256_8 design.lvs.v} blackbox
......@@ -13,6 +13,7 @@ name: netgen-lvs-def
inputs:
- adk
- design_extracted.spice
- design.lvs.v
- design.flatbuslvs.v
outputs:
......@@ -27,6 +28,7 @@ parameters:
commands:
# - v2lvs -i -lsp inputs/adk/stdcells.spi -s inputs/adk/stdcells.spi -lsp inputs/*.sp -s inputs/*.sp -v inputs/design.flatbuslvs.v -o design_lvs.spice
# - cat inputs/adk/stdcells.v inputs/design.lvs.v > design.lvs.v # EXPERIMENT
- cat inputs/adk/netgen_setup.tcl blackbox.tcl > netgen_blackbox_setup.tcl
- sh run_lvs.sh
# netgen -batch lvs "inputs/design_extracted.spice "$design_name"" "design.lvs.v "$design_name"" netgen_blackbox_setup.tcl outputs/lvs_results.log
netgen -batch lvs "inputs/design_extracted.spice "$design_name"" "inputs/design.lvs.v "$design_name"" netgen_blackbox_setup.tcl outputs/lvs_results.log
# Set up SRAM instances as black-box cells
model {sky130_sram_1kbyte_1rw1r_32x256_8 inputs/design_extracted.spice} blackbox
model {sky130_sram_1kbyte_1rw1r_32x256_8 design_lvs.spice} blackbox
model {sky130_sram_1kbyte_1rw1r_32x256_8 inputs/design.lvs.v} blackbox
......@@ -28,6 +28,6 @@ parameters:
commands:
- cat inputs/adk/netgen_setup.tcl blackbox.tcl > netgen_blackbox_setup.tcl
#- cat inputs/adk/netgen_setup.tcl > netgen_blackbox_setup.tcl
# - cat inputs/design.lvs.v inputs/adk/stdcells.v > design.lvs.v
- sh run_lvs.sh
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