add custom pt-timing-signoff node

GcdUnit/design/synopsys-pt-timing-signoff/configure.yml

+#=========================================================================
+# Synopsys PT Timing Signoff
+#=========================================================================
+# Author      : Alex Carsello
+# Date        : January 31, 2020
+# Modified by : Allen Pan
+# Date        : March 13, 2022
+
+name: synopsys-pt-timing-signoff
+
+#-------------------------------------------------------------------------
+# Inputs and Outputs
+#-------------------------------------------------------------------------
+
+# We will also get SPEF files for any blocks in the design.
+# These will be added as inputs in construct.py.
+inputs:
+  - adk
+  - design.vcs.v
+  - design.pt.sdc
+  - design.spef.gz
+
+outputs:
+  - design.sdf
+
+#-------------------------------------------------------------------------
+# Commands
+#-------------------------------------------------------------------------
+
+commands:
+  - mkdir -p reports
+  - pt_shell -file pt.tcl
+  - mkdir -p outputs && cd outputs
+  - ln -sf ../design.sdf design.sdf
+
+#-------------------------------------------------------------------------
+# Parameters
+#-------------------------------------------------------------------------
+
+parameters:
+  design_name: undefined
+

GcdUnit/design/synopsys-pt-timing-signoff/designer_interface.tcl

+#=========================================================================
+# designer_interface.tcl
+#=========================================================================
+# The designer_interface.tcl file is the first script run by PT (see the
+# top of pt.tcl). It is the interface that connects the scripts with
+# the following:
+#
+# - ASIC design kit
+# - Build system variables
+#
+# Author : Christopher Torng
+# Date   : May 20, 2019
+
+#-------------------------------------------------------------------------
+# Interface to the ASIC design kit
+#-------------------------------------------------------------------------
+
+set pt_additional_search_path   inputs/adk
+set pt_target_libraries         inputs/adk/stdcells.db
+set pt_extra_link_libraries     [lsort [glob -nocomplain inputs/*.db]]
+
+#-------------------------------------------------------------------------
+# Interface to the build system
+#-------------------------------------------------------------------------
+
+set pt_design_name              $::env(design_name)
+
+set pt_gl_netlist               [lsort [glob -nocomplain inputs/*.vcs.v]]
+set pt_sdc                      [lsort [glob -nocomplain inputs/*.pt.sdc]]
+set pt_spef                     [lsort [glob -nocomplain inputs/*.spef.gz]]
+
+puts "done"
+

GcdUnit/design/synopsys-pt-timing-signoff/pt.tcl

+#=========================================================================
+# reporting.tcl
+#=========================================================================
+# Final reports
+#
+# Author      : Alex Carsello
+# Date        : November 15, 2021
+# Modified by : Allen Pan
+# Date        : March 13, 2022
+#
+
+source -echo -verbose scripts/read_design.tcl
+
+# Please do not modify the sdir variable.
+# Doing so may cause script to fail.
+set sdir "." 
+
+set report_default_significant_digits 3
+
+##################################################################
+#    Constraint Analysis Section
+##################################################################
+check_constraints -verbose > reports/check_constraints.report
+
+##################################################################
+#    Update_timing and check_timing Section                      #
+##################################################################
+
+update_timing -full
+
+report_disable_timing > reports/report_disabled_timing.report
+
+check_timing -verbose > reports/check_timing.report
+
+##################################################################
+#    Report_timing Section                                       #
+##################################################################
+report_global_timing > reports/report_global_timing.report
+
+report_clock -skew -attribute > reports/report_clock.report 
+
+report_analysis_coverage -status_details untested > reports/report_analysis_coverage.report
+
+report_timing \
+  -crosstalk_delta \
+  -slack_lesser_than 10.0 \
+  -max_paths 100 \
+  -pba_mode exhaustive \
+  -delay max \
+  -nosplit \
+  -input_pins \
+  -nets \
+  -transition_time \
+  -sort_by slack \
+  > reports/$::env(design_name).timing.setup.rpt
+
+report_timing \
+    -crosstalk_delta \
+    -slack_lesser_than 10.0 \
+    -max_paths 100 \
+    -pba_mode exhaustive \
+    -delay max \
+    -nosplit \
+    -input_pins \
+    -nets \
+    -transition_time \
+    -path_type full_clock_expanded \
+    -sort_by slack \
+    > reports/$::env(design_name).timing.full_clock.setup.rpt
+
+report_timing \
+    -crosstalk_delta \
+    -slack_lesser_than 10.0 \
+    -max_paths 100 \
+    -pba_mode exhaustive \
+    -delay min \
+    -nosplit \
+    -input_pins \
+    -nets \
+    -transition_time \
+    -sort_by slack \
+    > reports/$::env(design_name).timing.hold.rpt
+
+report_timing \
+  -crosstalk_delta \
+  -slack_lesser_than 10.0 \
+  -max_paths 100 \
+  -pba_mode exhaustive \
+  -delay min \
+  -nosplit \
+  -input_pins \
+  -nets \
+  -transition_time \
+  -path_type full_clock_expanded \
+  -sort_by slack \
+  > reports/$::env(design_name).timing.full_clock.hold.rpt
+
+write_sdf -significant_digits 6 design.sdf
+
+save_session $::env(design_name)_session
+
+exit
+

GcdUnit/design/synopsys-pt-timing-signoff/scripts/read_design.tcl

+#-------------------------------------------------------------------------
+# Designer interface
+#-------------------------------------------------------------------------
+# Source the designer interface script, which sets up variables from the
+# build system, sets up ASIC design kit variables, etc.
+
+source -echo -verbose designer_interface.tcl
+
+#-------------------------------------------------------------------------
+# Setup
+#-------------------------------------------------------------------------
+
+# Set up paths and libraries
+
+set_app_var search_path      ". $pt_additional_search_path $search_path"
+set_app_var target_library   $ptpx_target_libraries
+set_app_var link_library     "* $pt_target_libraries $pt_extra_link_libraries"
+
+#-------------------------------------------------------------------------
+# Read design
+#-------------------------------------------------------------------------
+
+# Read and link the design
+
+read_verilog   $pt_gl_netlist
+
+current_design $pt_design_name
+
+link_design
+
+# Read in the SDC and parasitics
+
+read_sdc -echo $pt_sdc
+
+set_propagated_clock [all_clocks]
+
+read_parasitics -format spef $pt_spef

SramUnit/design/synopsys-pt-timing-signoff/configure.yml

+#=========================================================================
+# Synopsys PT Timing Signoff
+#=========================================================================
+# Author      : Alex Carsello
+# Date        : January 31, 2020
+# Modified by : Allen Pan
+# Date        : March 13, 2022
+
+name: synopsys-pt-timing-signoff
+
+#-------------------------------------------------------------------------
+# Inputs and Outputs
+#-------------------------------------------------------------------------
+
+# We will also get SPEF files for any blocks in the design.
+# These will be added as inputs in construct.py.
+inputs:
+  - adk
+  - design.vcs.v
+  - design.pt.sdc
+  - design.spef.gz
+
+outputs:
+  - design.sdf
+
+#-------------------------------------------------------------------------
+# Commands
+#-------------------------------------------------------------------------
+
+commands:
+  - mkdir -p reports
+  - pt_shell -file pt.tcl
+  - mkdir -p outputs && cd outputs
+  - ln -sf ../design.sdf design.sdf
+
+#-------------------------------------------------------------------------
+# Parameters
+#-------------------------------------------------------------------------
+
+parameters:
+  design_name: undefined
+

SramUnit/design/synopsys-pt-timing-signoff/designer_interface.tcl

+#=========================================================================
+# designer_interface.tcl
+#=========================================================================
+# The designer_interface.tcl file is the first script run by PT (see the
+# top of pt.tcl). It is the interface that connects the scripts with
+# the following:
+#
+# - ASIC design kit
+# - Build system variables
+#
+# Author : Christopher Torng
+# Date   : May 20, 2019
+
+#-------------------------------------------------------------------------
+# Interface to the ASIC design kit
+#-------------------------------------------------------------------------
+
+set pt_additional_search_path   inputs/adk
+set pt_target_libraries         inputs/adk/stdcells.db
+set pt_extra_link_libraries     [lsort [glob -nocomplain inputs/*.db]]
+
+#-------------------------------------------------------------------------
+# Interface to the build system
+#-------------------------------------------------------------------------
+
+set pt_design_name              $::env(design_name)
+
+set pt_gl_netlist               [lsort [glob -nocomplain inputs/*.vcs.v]]
+set pt_sdc                      [lsort [glob -nocomplain inputs/*.pt.sdc]]
+set pt_spef                     [lsort [glob -nocomplain inputs/*.spef.gz]]
+
+puts "done"
+

SramUnit/design/synopsys-pt-timing-signoff/pt.tcl

+#=========================================================================
+# reporting.tcl
+#=========================================================================
+# Final reports
+#
+# Author      : Alex Carsello
+# Date        : November 15, 2021
+# Modified by : Allen Pan
+# Date        : March 13, 2022
+#
+
+source -echo -verbose scripts/read_design.tcl
+
+# Please do not modify the sdir variable.
+# Doing so may cause script to fail.
+set sdir "." 
+
+set report_default_significant_digits 3
+
+##################################################################
+#    Constraint Analysis Section
+##################################################################
+check_constraints -verbose > reports/check_constraints.report
+
+##################################################################
+#    Update_timing and check_timing Section                      #
+##################################################################
+
+update_timing -full
+
+report_disable_timing > reports/report_disabled_timing.report
+
+check_timing -verbose > reports/check_timing.report
+
+##################################################################
+#    Report_timing Section                                       #
+##################################################################
+report_global_timing > reports/report_global_timing.report
+
+report_clock -skew -attribute > reports/report_clock.report 
+
+report_analysis_coverage -status_details untested > reports/report_analysis_coverage.report
+
+report_timing \
+  -crosstalk_delta \
+  -slack_lesser_than 10.0 \
+  -max_paths 100 \
+  -pba_mode exhaustive \
+  -delay max \
+  -nosplit \
+  -input_pins \
+  -nets \
+  -transition_time \
+  -sort_by slack \
+  > reports/$::env(design_name).timing.setup.rpt
+
+report_timing \
+    -crosstalk_delta \
+    -slack_lesser_than 10.0 \
+    -max_paths 100 \
+    -pba_mode exhaustive \
+    -delay max \
+    -nosplit \
+    -input_pins \
+    -nets \
+    -transition_time \
+    -path_type full_clock_expanded \
+    -sort_by slack \
+    > reports/$::env(design_name).timing.full_clock.setup.rpt
+
+report_timing \
+    -crosstalk_delta \
+    -slack_lesser_than 10.0 \
+    -max_paths 100 \
+    -pba_mode exhaustive \
+    -delay min \
+    -nosplit \
+    -input_pins \
+    -nets \
+    -transition_time \
+    -sort_by slack \
+    > reports/$::env(design_name).timing.hold.rpt
+
+report_timing \
+  -crosstalk_delta \
+  -slack_lesser_than 10.0 \
+  -max_paths 100 \
+  -pba_mode exhaustive \
+  -delay min \
+  -nosplit \
+  -input_pins \
+  -nets \
+  -transition_time \
+  -path_type full_clock_expanded \
+  -sort_by slack \
+  > reports/$::env(design_name).timing.full_clock.hold.rpt
+
+write_sdf -significant_digits 6 design.sdf
+
+save_session $::env(design_name)_session
+
+exit
+

SramUnit/design/synopsys-pt-timing-signoff/scripts/read_design.tcl

+#-------------------------------------------------------------------------
+# Designer interface
+#-------------------------------------------------------------------------
+# Source the designer interface script, which sets up variables from the
+# build system, sets up ASIC design kit variables, etc.
+
+source -echo -verbose designer_interface.tcl
+
+#-------------------------------------------------------------------------
+# Setup
+#-------------------------------------------------------------------------
+
+# Set up paths and libraries
+
+set_app_var search_path      ". $pt_additional_search_path $search_path"
+set_app_var target_library   $pt_target_libraries
+set_app_var link_library     "* $pt_target_libraries $pt_extra_link_libraries"
+
+#-------------------------------------------------------------------------
+# Read design
+#-------------------------------------------------------------------------
+
+# Read and link the design
+
+read_verilog   $pt_gl_netlist
+
+current_design $pt_design_name
+
+link_design
+
+# Read in the SDC and parasitics
+
+read_sdc -echo $pt_sdc
+
+set_propagated_clock [all_clocks]
+
+read_parasitics -format spef $pt_spef